I/O planning

I/O ring floor plan (Flip Chip)
  • I/O ring floor plan for different power supply groups
  • Determine placement based on requests from PCBs and packages
  • Compatible with area I/O such as Serdes
  • Reduces optimized I/O die size for pad limited chips
Automatic formation of optimal bumps
  • Automatic formation of optimal bumps allowing for I/O cell size and routability for each power supply group
  • Designation of signal, power and ground (SPG) ratios for each power supply group
  • Specification of the number of I/O rows for each power supply group
Automatic I/O cell placement
  • I/O cell placement allowing for routing distance to core cells
  • Also allows specification of I/O cell sequence for each power supply group
  • Automatic insertion of power supply and ground cells in accordance with the SPG ratio
  • I/O cell placement allowing for preassigned balls
  • Specification of routing areas for specific IO cells
I/O planning (WireBond)
  • Automatic formation of chip IO power supply groups
  • Automatic placement of IO cells and die pads for each power supply group
  • Automatic generation of power supply and ground pad cells, based on SPG ratios
  • Can be used with staggered die pad placement